Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an 8× TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.publishedVersionPeer reviewe

Design of Cyclic-Coupled Ring Oscillators with Guaranteed Maximal Phase Resolution

Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.acceptedVersionPeer reviewe

A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period

Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.acceptedVersionPeer reviewe

Energy-Efficient Cyclic-Coupled Ring Oscillator With Delay-Based Injection Locking

This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied to implement a cyclic-coupled ring oscillator (CCRO). Compared to an inverter-based CCRO with multi-drive injection, the proposed circuit eliminates the static short-circuit current drawn from the supply when drive circuits are in conflicting logic states, thus reducing the power consumption of the CCRO. The functionality and improved energy efficiency of the proposed circuit is demonstrated with circuit simulations of a CCRO implemented in a 28-nm CMOS process. The CCRO employing the proposed technique achieves up to 25% lower power consumption and over 20% lower power-delay product (PDP) compared to the inverter-based CCRO.This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied to implement a cyclic-coupled ring oscillator (CCRO). Compared to an inverter-based CCRO with multi-drive injection, the proposed circuit eliminates the static short-circuit current drawn from the supply when drive circuits are in conflicting logic states, thus reducing the power consumption of the CCRO. The functionality and improved energy efficiency of the proposed circuit is demonstrated with circuit simulations of a CCRO implemented in a 28-nm CMOS process. The CCRO employing the proposed technique achieves up to 25% lower power consumption and over 20% lower power-delay product (PDP) compared to the inverter-based CCRO.publishedVersionPeer reviewe

Signal Processing in Portable Biopotential Acquisition Systems

Signal acquisition for biomedical applications is a challenging subject with increasing demands in fidelity. Modern biomedical systems require flexibility, portability and reliability of the measurement equipment. Implants and wearable modules are becoming the main focus as the future diagnostic tools. The miniaturization of high-precision equipment involves numerous important trade-offs that have to be addressed in order to meet the imposed requirements. Biopotential signal processing happens in low frequency bands and involves detection of various temporal and spectral features. Relatively small amplitude and inaccessible nature of the signal sources require advanced techniques in offset cancellation and noise filtering. With careful design considerations it is possible to take advantage of the properties of the signal and minimize the processing required to extract the vital information from a patient body in a most convenient way. This work presents a practical implementation of biomedical signal processing chain in embedded cardiogram monitoring system. The tasks of signal acquisition, postprocessing, and out-streaming the signal are thoroughly addressed. The analysis of signal processing techniques that can be applied to encephalogram readings was performed, and the custom wireless streaming protocol was tailored for use with sub-dermal implants. The data handling methods that were studied in both cases give new insights on the related hardware challenges

Adaptive Channel Equalization : Multicore Processor Implementation

Advanced telecommunication techniques are more and more relying on the digital processing power that is needed for the signal demodulation and data recovery. In order to assess the practicability of concurrent signal processing in the field of communication, this project was focused on developing the adaptive signal filtering application on a distributed processor system. To prove and evaluate this concept, different versions of the fundamental and robust Least Mean Squares adaptive filter were implemented on a multi-core digital signal processor. Developed applications were tested by streaming the simulated digital transmission data to the device via Ethernet. Algorithm benchmark results are compared in terms of adaptation rate and execution speed. The parallelized version of the adaptive algorithm has shown promising results in terms of convergence and the workload distribution while its execution time is still inferior to the single-processor applications. Considering that only the most essential device functionality was used, there is a big room for improvement and optimization. The algorithm evaluation system established in the project can be reused for other concepts and related teaching

Sub-1 V output-capacitor-less low-dropout regulator with two compensation amplifiers for enhanced power supply rejection

Funding Information: ACKNOWLEDGMENT This work has been funded by Academy of Finland, project number 269196. Publisher Copyright: © 2020 IEEEIn this paper we propose two methods to boost the power supply rejection (PSR) of an output-capacitor-less low-dropout regulator (LDO). Our LDO is targeted for low-power system-on-chip applications, such as medical electronics, RFIDs, and IoT devices, where applied energy harvesting techniques induce large voltage ripple to supply line, thus requiring high PSR out of the LDO. The regulator utilizes a feed-forward path through the amplifier power supply rail to pass-transistor gate. Furthermore it includes a feed-forward amplifier to improve the frequency response and a feedback amplifier to stabilize the LDO, eliminating the need for an area consuming compensation capacitor. The proposed LDO is implemented in 28-nm CMOS technology. It supplies 700-mV output level with a current range of 0-5 mA and a 100-mV dropout voltage. The three amplifiers within our LDO consume only a total of 13 μA, thus regardless of increased complexity, high current efficiency of 99.74% is maintained. At the nominal load of 1 mA, low-frequency PSR reaches a value of -97 dB and at the high-frequency range of 1-20 MHz PSR is boosted to remain below -20 dB and the region of 3-10 MHz below -30 dB.Peer reviewe

A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators

This paper describes a configurable hysteresis comparator for asynchronous sigma-delta modulators (ASDM). The proposed comparator provides coarse and fine tuning options for configuring the loop delay and hence the frequency of an ASDM. The post-layout simulation of the comparator implemented in a 28 nm FDSOI process shows that the comparator provides hysteresis voltage range of ±(1 to 15.3) mV while consuming 36.8 nW to 4.4 uW from 0.7 V supply, which enables configurable ASDM center-frequency in the range of 100 kHz to 6 MHz.Peer reviewe

A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period

Publisher Copyright: © 2022 IEEE.Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.Peer reviewe

Design of Cyclic-Coupled Ring Oscillators with Guaranteed Maximal Phase Resolution

Publisher Copyright: © 2022 IEEE.Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.Peer reviewe